HMC704LP4E【PDF 27/44 页】IC FRACT-N PLL 16BIT 24QFN

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HMC704LP4E

v03.1211

8 GHz fractionaL-n PLL

For price, delivery, and to place orders: Hittite Microwave Corporation,20 Alpha Road, Chelmsford, MA 01824

Phone: 978-250-3343

Fax: 978-250-3373

Order On-line at www.hittite.com

Application Support: Phone: 978-250-3343 or apps@hittite.com

open Mode - Serial Port WritE operation

AVDD = DVDD = 3.3V +/-10%, AGND = DGND = 0V

table 11. SPi open Mode - Write timing characteristics

Parameter

Conditions

Min.

Typ.

Max.

Units

sDI setup time

sDI hold time

sEN low duration

sEN high duration

sCLK 32 Rising Edge to sEN Rising Edge

serial port Clock speed

MHz

A typical WRITE cycle is shown in Figure 38.

a. The Master (host) places 24 bit data, d23:d0, MsB first, on sDI on the first 24 falling edges of sCLK.

b. the slave (PLL) shifts in data on sDI on the first 24 rising edges of sCLK

c. Master places 5 bit register address to be written to, r4:r0, MsB first, on the next 5 falling edges of

sCLK (25-29)

d. slave shifts the register bits on the next 5 rising edges of sCLK (25-29).

e. Master places 3 bit chip address, a2:a0, MsB first, on the next 3 falling edges of sCLK (30-32).

Hittite reserves chip address a2:a0 = 000 for all RF PLL-VCOs.

slave shifts the chip address bits on the next 3 rising edges of sCLK (30-32).

g. Master asserts sEN after the 32nd rising edge of sCLK.

h. slave registers the sDI data on the rising edge of sEN.

Master clears sEN to complete the WRITE cycle.

Figure 38. Open Mode - Serial Port Timing Diagram - WRITE

sCLK

sDI

d22

sEN

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